1 of 8 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? unlimited write cycles ? low - power cmos operation ? read and write access times of 100ns ? lithium energy sour ce is electrically disconnected to retain freshness until power is applied for the first time ? optional industrial (ind) temperature range of -40 c to +85 c ? jedec standard 32 - pin dip package pin assignment pin description a0 Ca17 - address inputs dq0 C dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+3.3v) gnd - ground nc - no connect description the ds1249w 2048kb nonvolatile (nv) srams are 2,097,152 - bit, fully static, nv srams organized as 262,144 words by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry that constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is un conditionally enabled to prevent data corruption. there is no limit on the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing. ds1249w 3.3v 2048kb nonvolatile sram 19 - 5633; rev 11/10 www.maxim - ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 32 - pin encapsulated package 740mil extended a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 nc dq2 gnd 15 16 18 17 dq4 dq3 downloaded from: http:///
ds1249w 2 of 8 read mode the ds1249 devices execute a read cycle whenever we (write en able) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 18 addres s inputs (a 0 C a 17 ) defines which of the 262,144 bytes of data is accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providi ng that ce and oe access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later - occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe f or oe rather than t acc . write mode the ds1249 executes a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the w rite cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention . however, if the output drivers are enabled ( ce and oe active), then we will disable the outputs in t odw from its falling edge. data - retention mode the ds1249w provides full functional capabi lity for v cc greater than 3.0 volts and write protects by 2.8v. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatical ly write protects themselves, all inputs become dont care, and all ou tputs become high impedance. as v cc falls below approximately 2.5v, a power - switching circuit connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 2.5v, the power - switching circuit connects external v cc to the ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 3.0v. freshness seal each ds1249 device is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for battery backup operation. downloaded from: http:///
ds1249w 3 of 8 absolute maximum ratings voltage on any pin r elative to ground - 0.3v to +4.6v operating temperature range commercial: 0c to +70c industrial: - 40c to +85c storage temperature range - 40c to +85c lead temperature (soldering, 10 s) +260c note: edip is wave or hand soldered only. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum r ating conditions for extended periods of time ma y affect reliability. r ecommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes power - supply voltage v cc 3.0 3.3 3.6 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.4 v dc electrical characteristics (t a : see note 10; v cc = 3.3v 0.3v) parameter symbol min typ max units notes input leakage current i il -2.0 +2.0 a i/o leakage current ce v ih v cc i io -2.0 +2.0 a output current at 2.2v i oh -1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 150 250 a standby current ce = v cc - 0.2v i ccs2 100 150 a operating current i cco1 50 ma write protection voltage v tp 2.8 2.9 3.0 v capacitanc e (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 10 20 pf input/output capacitance c i/o 10 20 pf downloaded from: http:///
ds1249w 4 of 8 ac electrical characteristics (t a : see note 10; v cc = 3.3v 0.3v) parameter symbol DS1249W-100 units notes min max rea d cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns ce to output valid t co 100 ns oe or ce to output active t coe 5 ns 5 output high -z from deselection t od 35 ns 5 output hold from address change t oh 5 ns write cycle time t wc 100 ns write pulse width t wp 75 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 20 ns ns 12 13 output high - z from we t odw 35 ns 5 output active from we t oew 5 ns 5 data setup time t ds 40 ns 4 data hold time t dh1 t dh2 0 20 ns ns 12 13 read cycle see note 1 downloaded from: http:///
ds1249w 5 of 8 write cycle 1 see notes 2, 3, 4, 6, 7, 8, and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8, and 13 downloaded from: http:///
ds1249w 6 of 8 power - down/power - up condition see note 11 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detec t to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a = +25 c) parameter symbol min typ max units notes expected data - retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance s tate. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the ea rlier of ce or we going high. 5. these parameters are sampled with a 5pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition in write cycle 1, the output buffers remain in a high - impedance state during this period. downloaded from: http:///
ds1249w 7 of 8 7. if the ce high transition occurs prior to, or simultaneously with, the we high transition, the output buff ers remain in a high - impedance state during this period. 8. if we is low or the we low transition occurs prior to, or simultaneously with, the ce low transition, the output buffers remain in a hig h- impedance state during this period. 9. each ds1249w has a built - in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is firs t applied by the user. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, this range is 0 c to +70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power - down condition , the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. ds1249 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions ac test conditions outputs open output load: 100pf + 1ttl gate cycle = 200ns for operating current input pulse levels: 0 to 2.7v all voltages are referenced to ground timing measurement reference lev els input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply tolerance pin - package speed grade (ns) DS1249W-100# 0c to +70c 3.3v 0.3v 32 740 edip 100 DS1249W-100ind# - 40c to +85c 3.3v 0.3v 32 740 edip 100 # denotes a rohs - compliant device tha t may include lead(pb) that is exempt under the rohs requirements. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs st atus. package type package code o utline no. land pattern no. 32 edip mdt3 2#7 21-0245 downloaded from: http:///
ds1249w 8 of 8 revision history revision date description pages changed 11/10 updated the st orage information, soldering temperature, and lead temperature information in the absolute maximum ratings section; removed the -15 0 min/max information from the ac electrical characteristics table; updated the ordering information table (removed - 15 0 part s and leaded -10 0 parts) ; add ed the package information table 1, 3, 4, 7 downloaded from: http:///
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